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SN74LS377 Octal D Flip-Flop with Enable
The SN74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable.
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* * * * *
8-Bit High Speed Parallel Registers Positive Edge-Triggered D-Type Flip Flops Fully Buffered Common Clock and Enable Inputs True and Complement Outputs Input Clamp Diodes Limit High Speed Termination Effects
LOW POWER SCHOTTKY
GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current - High Output Current - Low Min 4.75 0 Typ 5.0 25 Max 5.25 70 - 0.4 8.0 Unit V C mA mA
20 1
PLASTIC N SUFFIX CASE 738
20 1
SOIC DW SUFFIX CASE 751D
ORDERING INFORMATION
Device SN74LS377N SN74LS377DW Package 16 Pin DIP 16 Pin Shipping 1440 Units/Box 2500/Tape & Reel
(c) Semiconductor Components Industries, LLC, 1999
1
December, 1999 - Rev. 6
Publication Order Number: SN74LS377/D
SN74LS377
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC 20
Q7 19
D7 18
D6 17
Q6 16
Q5 15
D5 14
D4 13
Q4 12
CP 11 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.
1 E
2 Q0
3 D0
4 D1
5 Q1
6 Q2
7 D2
8 D3
9 Q3
10 GND
LOADING (Note a) PIN NAMES E D0 - D3 CP Q0 - Q3 Q0 - Q3 Enable (Active LOW) Input Data Inputs Clock (Active HIGH Going Edge) Input True Outputs Complemented Outputs HIGH 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 10 U.L. LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 U.L. 5 U.L.
NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.
LOGIC DIAGRAM
3 4 7 8 13 14 17 18
D0 E ENABLE
1
D1
D2
D3
D4
D5
D6
D7
CP CLOCK
11
CP D Q
CP D Q
CP D Q
CP D Q
CP D Q
CP D Q
CP D Q
CP D Q
Q0
2
Q1
5
Q2
6
Q3
9
Q4
12
Q5
15
Q6
16
Q7
19
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SN74LS377
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.7 - 0.65 3.5 0.25 VO OL Output LOW Voltage 0.35 Input HIGH Current Input LOW Current Short Circuit Current (Note 1) Power Supply Current - 20 0.5 20 0.1 - 0.4 - 100 28 V A mA mA mA mA 0.4 Min 2.0 0.8 - 1.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = - 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table
IIH IIL IOS ICC
VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX, NOTE 1
NOTE: With all inputs open and GND applied to all data and enable inputs, ICC is measured after a momentary GND, then 4.5 V is applied to clock. Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V)
Limits Symbol fMAX tPLH tPHL Parameter Maximum Clock Frequency Propagation Delay, Clock to Output Min 30 Typ 40 17 18 27 27 Max Unit MHz ns Test Conditions VCC = 5 0 V 5.0 CL = 15 pF
AC SETUP REQUIREMENTS (TA = 25C, VCC = 5.0 V)
Limits Symbol tW ts ts th Parameter Any Pulse Width Data Setup Time Enable Setup Time Any Hold Time Inactive -- State Active -- State Min 20 20 10 25 5.0 Typ Max Unit ns ns ns ns ns VCC = 5.0 V Test Conditions
DEFINITION OF TERMS
SETUP TIME (ts) -- is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW-to-HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) -- is defined as the minimum time following the clock transition from LOW-to-HIGH that the
logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW-to-HIGH and still be recognized.
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SN74LS377
TRUTH TABLE
E H L L
L = LOW Voltage Level H = HIGH Voltage Level X = Immaterial
CP
Dn X H L
Qn No Change H L
Qn No Change L H
AC WAVEFORM
1/fmax CP 1.3 V ts(H) D OR E * 1.3 V tPLH Q 1.3 V th(H) ts(L) tW 1.3 V th(L) 1.3 V tPHL 1.3 V
*The shaded areas indicate when the input is permitted to change for predictable output performance.
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SN74LS377
PACKAGE DIMENSIONS
N SUFFIX PLASTIC PACKAGE CASE 738-03 ISSUE E
-A-
20 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01
B
1 10
C
L
-T-
SEATING PLANE
K M E G F D
20 PL
N J 0.25 (0.010)
M 20 PL
0.25 (0.010) TA
M
M
TB
M
DIM A B C D E F G J K L M N
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SN74LS377
PACKAGE DIMENSIONS
D SUFFIX PLASTIC SOIC PACKAGE CASE 751D-05 ISSUE F
D
A
11 X 45 _
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
M
B
M
20
10X
0.25
E
1
10
h
20X
B 0.25
M
B TA
S
B
S
A
SEATING PLANE
DIM A A1 B C D E e H h L
L
18X
e
A1
q
T
C
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SN74LS377
Notes
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SN74LS377
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PUBLICATION ORDERING INFORMATION
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SN74LS377/D

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